Regviz

Espressif Systems /ESP32-S2 /TIMG0 /INT_ST_TIMERS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INT_ST_TIMERS

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S2/TIMG0/INT_ST_TIMERS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (T0_INT_ST)T0_INT_ST 0 (T1_INT_ST)T1_INT_ST 0 (WDT_INT_ST)WDT_INT_ST 0 (LACT_INT_ST)LACT_INT_ST

Description

Masked interrupt status

Fields

T0_INT_ST

The masked interrupt status bit for the TIMG_T0_INT interrupt.
T1_INT_ST

The masked interrupt status bit for the TIMG_T1_INT interrupt.
WDT_INT_ST

The masked interrupt status bit for the TIMG_WDT_INT interrupt.
LACT_INT_ST

The masked interrupt status bit for the TIMG_LACT_INT interrupt.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/espressif/svd